Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao

This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an application running on simulated hardware. When an application terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system

IEEE Transactions on Software Engineering 25(5), pages 619-632, sept/oct 1999, IEEE Computer Sosciety
title={Hierarchical simulation approach to accurate fault modeling for system dependability evaluation},
author={Kalbarczyk, Zbigniew and Iyer, Ravishankar K. and Ries, Gregory L. and Patel, Jaqdish U. and Lee, Myeong S. and Xiao, Yuxiao},
journal={IEEE Transactions on Software Engineering} ,
publisher ={IEEE Computer Sosciety}



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